IEEE standard Verilog hardware description language / sponsor, Design Automation Standards Committee of the IEEE Computer Society.
"The Verilog Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testi...
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| Language: | English |
| Published: |
New York :
Institute of Electrical and Electronics Engineers,
2001.
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| Subjects: | |
| Physical Description: | xi, 778 pages : illustrations ; 28 cm |
| Variant Title: |
Verilog hardware description language.
IEEE Std 1364-2001. [Other title] |
| Format: | Book |
| Summary: |
"The Verilog Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language." |
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| Note: | "Approved 17 March 2001, IEEE-SA Standards Board." "IEEE Std 1364-2001 (revision of IEEE Std 1364-1995)." |
| Call Number: | TK7885.7 .I5765 2001 |
| Bibliography Note: | Includes bibliographical references. |
| ISBN: | 0738128260 |
| Action Note: |
copy1 Committed to retain 20200101 20341231 MI-SPI http://www.mcls.org/engagement/mi-spi/ MiEM |