Transaction processing on modern hardware / Mohammad Sadoghi, Spyros Blanas.
The last decade has brought groundbreaking developments in transaction processing. This resurgence of an otherwise mature research area has spurred from the diminishing cost per GB of DRAM that allows many transaction processing workloads to be entirely memory-resident. This shift demanded a pause t...
| Uniform Title: | Synthesis digital library of engineering and computer science.
Synthesis lectures on data management ; #58. |
|---|---|
| Main Authors: | |
| Language: | English |
| Published: |
[San Rafael, California] :
Morgan & Claypool,
[2019]
|
| Series: | Synthesis digital library of engineering and computer science.
Synthesis lectures on data management ; #58. |
| Subjects: | |
| Online Access: | |
| Physical Description: | 1 PDF (xv, 112 pages) : illustrations (some color). |
| Format: | Electronic eBook |
MARC
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| 100 | 1 | |a Sadoghi, Mohammad, |e author. | |
| 245 | 1 | 0 | |a Transaction processing on modern hardware / |c Mohammad Sadoghi, Spyros Blanas. |
| 264 | 1 | |a [San Rafael, California] : |b Morgan & Claypool, |c [2019] | |
| 300 | |a 1 PDF (xv, 112 pages) : |b illustrations (some color). | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a electronic |2 isbdmedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a Synthesis lectures on data management, |x 2153-5418 ; |v #58 | |
| 500 | |a Part of: Synthesis digital library of engineering and computer science. | ||
| 504 | |a Includes bibliographical references (pages 105-119). | ||
| 505 | 0 | |a 1. Introduction -- 1.1. The shifting hardware landscape -- 1.2. Book outline | |
| 505 | 8 | |a 2. Transaction concepts -- 2.1. Overview -- 2.2. Acid properties -- 2.3. Concurrency control overview -- 2.4. Overview concurrency control protocols | |
| 505 | 8 | |a 3. Multi-version concurrency revisited -- 3.1. Optimistic concurrency -- 3.2. Pessimistic concurrency -- 3.3. Time-based concurrency -- 3.4. Multi-version storage model | |
| 505 | 8 | |a 4. Coordination-avoidance concurrency -- 4.1. Restrictive concurrency -- 4.2. Deterministic planning optimization | |
| 505 | 8 | |a 5. Novel transactional system architectures -- 5.1. Hardware-aware concurrency -- 5.2. HTAP : hybrid transactional and analytical processing | |
| 505 | 8 | |a 6. Hardware-assisted transactional utilities -- 6.1. Database partitioning -- 6.2. Database indexing | |
| 505 | 8 | |a 7. Transactions on heterogeneous hardware -- 7.1. Hardware accelerators -- 7.2. RDMA : remote direct memory access | |
| 505 | 8 | |a 8. Outlook : the era of hardware specialization and beyond -- 8.1. Scaling the network wall for distributed transaction processing -- 8.2. Near-data transaction processing -- 8.3. Blockchain : fault-tolerant distributed transactions. | |
| 520 | 3 | |a The last decade has brought groundbreaking developments in transaction processing. This resurgence of an otherwise mature research area has spurred from the diminishing cost per GB of DRAM that allows many transaction processing workloads to be entirely memory-resident. This shift demanded a pause to fundamentally rethink the architecture of database systems. The data storage lexicon has now expanded beyond spinning disks and RAID levels to include the cache hierarchy, memory consistency models, cache coherence and write invalidation costs, NUMA regions, and coherence domains. New memory technologies promise fast non-volatile storage and expose unchartered trade-offs for transactional durability, such as exploiting byte-addressable hot and cold storage through persistent programming that promotes simpler recovery protocols. In the meantime, the plateauing single-threaded processor performance has brought massive concurrency within a single node, first in the form of multi-core, and now with many-core and heterogeneous processors. The exciting possibility to reshape the storage, transaction, logging, and recovery layers of next-generation systems on emerging hardware have prompted the database research community to vigorously debate the trade-offs between specialized kernels that narrowly focus on transaction processing performance vs. designs that permit transactionally consistent data accesses from decision support and analytical workloads. In this book, we aim to classify and distill the new body of work on transaction processing that has surfaced in the last decade to navigate researchers and practitioners through this intricate research subject. | |
| 538 | |a Mode of access: World Wide Web. | ||
| 538 | |a System requirements: Adobe Acrobat Reader. | ||
| 588 | |a Title from PDF title page (viewed on April 2, 2019). | ||
| 650 | 0 | |a Transaction systems (Computer systems) |0 http://id.loc.gov/authorities/subjects/sh89002252 | |
| 653 | |a transaction processing | ||
| 653 | |a ACID semantics | ||
| 653 | |a consistency | ||
| 653 | |a isolation levels | ||
| 653 | |a concurrency controls | ||
| 653 | |a optimistic concurrency | ||
| 653 | |a pessimistic concurrency | ||
| 653 | |a multi-version concurrency control | ||
| 653 | |a hardware-conscious concurrency | ||
| 653 | |a HTAP | ||
| 653 | |a indexing | ||
| 653 | |a hardware acceleration | ||
| 653 | |a RDMA | ||
| 700 | 1 | |a Blanas, Spyros, |e author. |0 http://id.loc.gov/authorities/names/nb2017010160 | |
| 776 | 0 | 8 | |i Print version: |z 9781681735016 |z 9781681734996 |
| 830 | 0 | |a Synthesis digital library of engineering and computer science. |0 http://id.loc.gov/authorities/names/n2016188085 | |
| 830 | 0 | |a Synthesis lectures on data management ; |v #58. |0 http://id.loc.gov/authorities/names/no2010037814 | |
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